1. Field of the Invention
The present invention relates to a test for contact openings of a semiconductor device. More particularly, it relates to a test for contact openings that may prevent contact failure by inspecting a wafer prepared in the semiconductor production line with an in-line scanning electron microscope (SEM) at certain points during the process for forming the contact opening. The process conditions for forming the contact openings is controlled using data obtained from the inspection.
2. Description of the Related Art
Generally, a contact hole or contact opening for a semiconductor device is formed by etching a predetermined region of an insulating layer to allow for electrical contact between internal elements or conductive layers of the device. Either a conductive metal for wiring, or a polysilicon material for forming a charge-storage plate of a condenser, is normally deposited in the contact hole.
FIG. 1 shows a sequence of forming a contact opening according to a conventional process. First, in step S2, a contact photolithography process is carried out to form a pattern for the contact hole on a predetermined layer formed on a wafer. More specifically, during step S2, a photoresist is coated on the predetermined layer on the wafer. Then, a contact opening region, where a contact hole is to be formed, is exposed to light and developed so that the photoresist in the contact opening region is removed to thereby form an etching mask for the formation of a contact hole. An insulating layer is commonly used as the abovementioned predetermined layer.
A contact etching process for the contact opening is performed in step S4. A contact hole of predetermined profile is thus formed in the predetermined layer. Subsequently, in step S6, a conductive metal is deposited onto the predetermined layer having the contact hole. The metal layer formed through the deposition process of S6 is etched to a predetermined pattern for wiring or condenser formation through a conductive layer photolithography process (step S8) and a conductive layer etching process (step S10).
A metallization process and a passivation process (not shown) are successively carried out to complete the steps in the manufacture of the semiconductor device.
In step S12, the completed integrated circuit (IC) wafer undergoes an electrical die sorting (EDS) test which inspects the electrical characteristics of each chip. The chips are considered substandard when the contact holes are not precisely formed. Contact failures are a principal cause of semiconductor device malfunctions. Such contact failures can not be fixed at this late stage and the chip must be discarded, resulting in waste, inefficiency, and higher semiconductor production costs.
The contact failures occur for a variety of reasons. For example, a failure may occur when the photoresist is not completely removed within in the contact hole pattern through the contact photolithography process of step S2. Also, a failure may occur when the insulating layer remains within the contact hole as a result of an incomplete contact opening etching process of step S4.
The equipment or process conditions for performing the contact photolithography process in step S2 or the contact opening etching process in step S4 is checked and modified upon detection of an abnormality by the EDS test in step S12. In that way, enhanced process control and increased IC yields may be achieved.
However, using conventional techniques, it generally takes about two to three months from the time the EDS test identifies a failure until a remedy for the contact opening failure is effected. During this long period, the manufacturing yield is reduced and process efficiency is greatly reduced.